1. Field of the Invention
The present invention relates to a pixel electrode structure, and more particularly, to a pixel electrode structure with high display quality.
2. Description of the Prior Art
Please refer to FIG. 1. In a conventional active matrix type liquid crystal display (LCD), each pixel of a single-gate circuit structure includes a thin-film transistor 10. A gate electrode of the thin film transistor 10 is connected to a horizontal gate line 12, a source electrode of the thin film transistor 10 is connected to a vertical data line 14, and a drain electrode of the thin film transistor 10 is connected to a pixel electrode. Each thin film transistor 10 in a same row is connected to a different data line 14.
In the following, a basic method of operating the conventional single-gate circuit structure is described. Each thin film transistor 10 in a same horizontal row has a gate electrode electrically connected to a same gate line 12, such that the gate electrodes are also electrically connected to each other. Thus, voltages applied to the gate electrodes of the thin film transistors electrically connected to the same gate line 12 are approximately equal, and are changed together. If a sufficiently large positive voltage is applied to a gate line 12, all thin film transistors 10 connected to the gate line 12 will be turned on. The pixel electrodes disposed along the gate line 12 are electrically connected to corresponding vertical data lines 14, and corresponding data signals are transferred into the vertical data lines 14 to charge the corresponding pixel electrodes to appropriate voltages. Next, a sufficiently large negative voltage is applied to the gate electrodes to turn off the thin film transistors 10. During the period when the thin film transistors 10 are turned off, the electric charges of the data signals are thus stored in the liquid crystal capacitors until next data signals are to be written. The next horizontal gate line 12 is then turned on, and the corresponding data signals are transferred into the corresponding data lines 14. As a result, the data signals of a whole frame can be written into the thin film transistors 10 in sequence according to the aforementioned method. Thereafter, the process of transferring the data signals can start again from the first gate line.
Because number of the plurality of data lines 14 is high, and the number of expensive source chips used is increasing accordingly, cost of the display panel is high in the aforementioned single-gate circuit structure. In order to reduce the cost, a dual-gate circuit structure is provided, as shown in FIG. 2. Each pair of adjacent columns of thin film transistors 16 share a same data line 18, so that the number of the data lines 18 can be reduced, and the number of the source chips can be accordingly reduced. Therefore, the manufacturing cost of the display panel is reduced due to the number of source chips used by the display panel being reduced. In addition, a dummy line 20 is disposed between each two adjacent data lines 18 to reduce crosstalk resulting from electromagnetic interference (EMI) caused in pixels corresponding to the two adjacent columns between the two adjacent data lines 18 in the display panel. The dummy line 20 receives a data signal having polarity opposite that of the data line 18, to improve display quality of the panel.
As shown in FIG. 3, in the circuit layout of the aforementioned prior art, a common line 22 is an opaque metal layer disposed under an electrode layer 24 in a transmissive region. Due to the common line 22 partially shielding the electrode layer 24, area of the transmissive region of an electrode layer 24 is reduced, and aperture ratio of the whole display panel is reduced.